ÙQ`Z)ooIs@WDՀ}ONC7=ZPVkjޫP]t2&BZ9r̖E8t[1ݍcF @({ tQ8&|zh}aLYHy+*3[)Z :t>l]@Qq8oq+gO >qž`wJe id!%?(3?4;D(B ΂B+8-Sũ[K1ZI˖ˈG;g]AGjWH3rV9,y +D ۫ -nb/H\cLc}:j R.3&2;}Qp hO` @fb?_&xr8QJHY&52!5ɧGkhZצl:I~'ޢYrLbR±HqI75fA+nn ۘr~!ŭ %q@T?Yjyoo#lVBph$})f_s ^g>ygBC.# Y#@/76a1)C%ηaeP0lBWcK8u-Lćq'#X(vs> r%J+d2%P])s`C4dMsi@T&_6=ҋo4zf4<#+}eO#qM 5J&iG+eࠝ$;1 ZǶn{pN+Nid' uV;wCU(k6kBWIV D)7pѳ3ZK~0 I+ sJ#ϤDÀ1>l7Ml G=(;%C%e䬛#[4Zt.al Logic (PITL) which is better suited than PTL for sequentially combining and decomposing formulas. Consequently, we can articulate issues in PTL model construction of equal relevance in more conventional analyses but normally only considered at the metalevel. We also describe a decision procedure based on Binary Decision Diagrams. Beyond the specific issues involving PTL, the research is a significant application of ITL and interval-based reasoning and illustrates a general approach to formally reasoning about sequential and parallel behaviour in discrete linear time. The work also includes some interesting representation theorems. In addition, it has relevance to hardware description and verification since the specification languages PSL/Sugar (now IEEE standard 1850) and 'temporal e' (part of IEEE candidate standard 1647) both contain temporal constructs concerning intervals of time as does the related SystemVerilog Assertion language contained in SystemVerilog, an extension of the IEEE 1364-2001 Verilog language. BCCCC